1 CMOS technology scaling and its implications

In these five decades after Gordon Moore propounded Moore’s Law in 1965 [1], the semiconductor industry has been continuously growing in accordance with his expectations, and we are now facing sub-10-nm feature size transistors. Thanks to the immense intelligence devoted to pushing this exponential technology scaling, the transistor count on a single microprocessor chip almost doubles every 2 years, as shown in Figure 1.1, and this trend has even been accelerated in recent years. As a consequence, after the Cray-1 was marketed as the world’s fastest computer in 1976, we now have almost 1000-times improved performance on only a single 300 mm chip with a billion of integrated transistors operating with a 50-times faster clock [2, 3]. Besides the tremendous benefits of transistor technology scaling, we have been facing a lot of circuit design implications and problems with these scaled transistors. Due to a lot of imperfections in both the devices and the fabrication processes, the difficulties of circuit design are ever-increasing, and it is almost impossible to build highly sophisticated VLSI systems without a set of calibration and digital/analog assisting techniques. This chapter first briefly looks over the fundamentals of scaling. Then we revisit several traditional scaling implications such as short-channel effects, which is followed